Modeling SiO2 Ion Impurities Aging in Insulated Gate Power Devices Under Temperature and Voltage Stress

Antonio E Ginart, Irfan N. Ali, Jose R. Celaya, Patrick W. Kalgren, Scott D. Poll, and Michael J. Roemer
Submission Type: 
Full Paper
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phmc_10_032.pdf410.05 KBOctober 7, 2010 - 7:21am

This paper presents a formal computational methodology to explain how the oxide in semiconductors age over time. The rearrangements in the oxide impurities are explained in the backdrop of the environmental and operational stress factors as they relate to voltages and temperatures. This paper also outlines the reliability theory behind the life expectancy of power semiconductors with insulted gate such as MOSFETs and IGBTs and discusses how accelerated stress factors relate to normal operational condition. The effects of aging are modeled and quantified by the modification of the value of gate-source capacitance. The power semiconductors undergo accelerated aging by thermo-electrical HALT methodology. Experimental results verified with thermoelectrically aged devices and the modification of parametric values are presented and compared with the model results.

Publication Control Number: 
032
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